For flash memory devices by using a single floating gate to store an electric charge, which represents data, a capacitance area (CAP) is generally added into the flash memory devices which has a cell area and a logical area. The film layer depositing on the newly added capacitance area is the same as the film layer of the control gate in the cell area, and there is a floating gate both above the active areas in the capacitance area and the cell area, and the material of the floating gate is polysilicon.
However, there is no a floating gate on the shallow trench isolation (STI) of the capacitance area, and the width of the STI in the capacitance area is larger than the width of the STI in the cell area. Thus, unlike in the cell area, the subsequent processes can't make the total thickness of the polysilicon layer on the STI in the capacitance area equal to the total thickness of the polysilicon layer on the active area by controlling the growth of the polysilicon.
Wherein, the total thickness of the polysilicon layer on the active area of the capacitance area is a sum of the thicknesses of the floating gate and the polysilicon growing on the floating gate, but the total thickness of the polysilicon layer above the STI is relatively small due to no floating gate. Such difference in the thickness becomes more distinct in the growth of the subsequent film layer, as shown in FIG. 1. Such height difference makes the process window subsequent for controlling the etching procedure of the gate become narrow, even disappear.
It can be seen from FIG. 1 that, the above thickness difference is the height difference between the floating gate and a silicon oxide filled shallow trench in the Flash wafer, wherein the silicon oxide filled shallow trench is in the STI.
To reduce the height difference, the height of the silicon oxide filled shallow trench in the capacitance area may be increased so as to make it identical to the height of the floating gate as far as possible. In the prior art, the following processes are adopted to adjust the height of the silicon oxide filled shallow trench in the capacitance area, and the processes are specifically shown in FIG. 2:
(1) As shown in FIG. 2A, after a STI in the cell area is finished, a STI etching of the logical area and the capacitance area are performed by using a mask Z1 and thus a Flash wafer containing the cell area, the logical area and the capacitance area is obtained. Each of the cell area, the logical area and the capacitance area includes a STI and an active area, and the STI is in a gap of the active area; a floating gate is located above the active area and the material of the floating gate is polysilicon; and the upper surface of the Flash wafer is planarized to obtain a flat silicon oxide filled shallow trench.
(2) As shown in FIGS. 2B and 2C, by protecting the logical area with a mask Z2, the silicon oxide filled shallow trench in the cell area and the capacitance area is etched with negative photoresist, so that in the cell area and the capacitance area, the silicon oxide filled shallow trench is lower than the height of the floating gate above the active area. The function adjustment of the cell area can be achieved by adjusting such height difference.
(3) As shown in FIG. 2D, an interlayer dielectric layer consisting of silicon oxide-silicon nitride-silicon oxide layers is filled on the upper surface of the above Flash wafer.
(4) As shown in FIG. 2E, the interlayer dielectric layer, the floating gate and a part of silicon oxide filled shallow trench in the logical area are removed by protecting the cell area and the capacitance area with a mask Z3, to obtain the Flash wafer in which the height of the silicon oxide filled shallow trench is lower than the floating gate in the cell area and the capacitance area.
In the above manufacturing procedure, the silicon oxide filled shallow trench in the cell area and the capacitance area are synchronously changed in height due to the restriction of the mask in the existing process. When the height of the silicon oxide filled shallow trench in the capacitance area is increased relative to the height of the floating gate, the height of the silicon oxide filled shallow trench in the cell area will be also increased relative to the height of the floating gate. However, such change in the cell area will weaken the coupling rate between the control gate and the floating gate, thereby influence the storing property.